1. Field of the Invention
The present invention generally relates to analog-to-digital converters and, more particularly, to a successive approximation analog-to-digital converter (hereinafter, referred to as a successive approximation A/D converter) capable of error correction. A successive approximation A/D converter is defined as an A/D converter effecting analog-to-digital conversion by determining a binary code bit by bit.
2. Description of the Related Art
A successive approximation A/D converter is well known in the art as an analog-to-digital converter for use in mechanical control such as servo control. FIG. 12 shows a construction of a 4-bit successive approximation A/D converter according to the related art. Referring to FIG. 12, the 4-bit successive approximation A/D converter comprises an analog input terminal 101, a conversion result output terminal 102, a sample and hold 103 (hereinafter, referred to as an S/H), a digital-to-analog converter 104 (hereinafter, referred to as a DAC), a ladder resistor (referred to as an SAR) 105, a 1-bit comparator 106 and a control circuit 107 provided with a latching function. The 1-bit comparator 106 is given its designation because it outputs a 1-bit conversion result to the control circuit 107 in one conversion cycle.
A description will now be given of the operation of each of the converter elements.
The S/H 103 having an input thereof connected to the analog input terminal 101 and an output thereof connected to the 1-bit comparator 106 holds an analog input voltage input via the analog input terminal 101 while the 1-bit comparator 106 is performing a comparison operation. The SAR 105 is comprised of a group of resistors for dividing an externally supplied or internally generated reference voltage in 16 steps (24=16) so as to output a voltage that serves as a reference in a comparison operation (hereinafter, simply referred to as a comparison reference voltage) to the DAC 104. The DAC 104 outputs to the 1-bit comparator 106 the comparison reference voltage produced by the SAR 105 or a comparison reference voltage produced on the basis of the comparison reference voltage produced by the SAR 105, in accordance with a control signal supplied from the control circuit 107. The 1-bit comparator 106 compares the analog input voltage held in the S/H 103 with the comparison reference voltage supplied from the DAC 104. The 1-bit comparator 106 converts a result of comparison into digital data so as to output the digital data to control circuit 107. The 1-bit comparator 106 outputs xe2x80x9c1xe2x80x9d as a conversion result when it is determined that the analog input voltage is higher than the comparison reference voltage and outputs xe2x80x9c0xe2x80x9d as a conversion result when it is determined that the analog input voltage is lower than the comparison reference voltage. The control circuit 107 latches the 1-bit conversion result output from the 1-bit comparator 206 and determines a voltage to be used as the comparison reference voltage in the subsequent comparison, based on the conversion result. The control circuit 107 outputs the control signal to the DAC 104 so as to set the determined voltage therein. When an entire conversion process is completed, the control circuit 107 outputs a final conversion result based on a 4-bit conversion result to the conversion result output terminal 102.
FIG. 13 shows a sequence of operations performed by the 4-bit successive approximation A/D converter according to the related art. A vertical scale 108 indicates 16 discrete values that the comparison reference voltage can take. A dotted line 109 indicates the analog input voltage. A solid line 110 indicates the comparison reference voltage subject to comparison with the analog input voltage by the 1-bit comparator 106. Binary values 111 indicate conversion results output in respective conversion cycles from the 1-bit comparator 106. Each of two-way arrows 112 indicates a conversion cycle.
A description will now be given of a sequence of a conversion operation.
In a bit 3 conversion cycle, voltage 8 is set by the SAR 105 and the DAC 104 as the comparison reference voltage. The level of voltage 8 is half that of an upper limit of the comparison reference voltage used in digital conversion of the analog input voltage. The 1-bit comparator 106 then compares the voltage 8 with the analog input voltage. Since the analog input voltage is higher in level than voltage 8, the 1-bit comparator 106 outputs xe2x80x9c1xe2x80x9d as the conversion result. The control circuit 107 latches the conversion result in the bit 3 conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. If the conversion result in the bit 3 conversion cycle is xe2x80x9c1xe2x80x9d, voltage 12 is set by the control signal. If the conversion result in the bit 3 conversion cycle is xe2x80x9c0xe2x80x9d, voltage 4 is set by the control signal. Since, in this case, the conversion result output from the 1-bit comparator 106 is xe2x80x9c1xe2x80x9d, voltage 12 is set as the comparison reference voltage in the subsequent comparison.
In a bit 2 conversion cycle, voltage 12 is set by the SAR 105 and the DAC 104 as the comparison reference voltage so that the 1-bit comparator 106 compares voltage 12 with the analog input voltage. Since the analog input voltage is higher in level than voltage 12, the 1-bit comparator 106 outputs xe2x80x9c1xe2x80x9d as the conversion result. The control circuit 107 latches the conversion result in the bit 2 conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. That is, the control circuit 107 outputs the control signal to the DAC 104 to set the comparison reference voltage to be used in a bit 1 conversion cycle, based on the latched conversion result in the bit 3 conversion cycle and the latched conversion result in the bit 2 conversion cycle. Assuming that the conversion result in the bit 3 conversion cycle is xe2x80x9c1xe2x80x9d, if the conversion result in the bit 2 conversion cycle is xe2x80x9c1xe2x80x9d, voltage 14 is set by the control signal; if the conversion result in the bit 2 conversion cycle is xe2x80x9c0xe2x80x9d, voltage 10 is set by the control signal. Since, in this case, the conversion result in the bit 2 conversion cycle is xe2x80x9c1xe2x80x9d, voltage 14 is set as the comparison reference voltage to be used in the subsequent comparison.
In the bit 1 conversion cycle, voltage 14 is set by the SAR 105 and the DAC 104 as the comparison reference voltage so that the 1-bit comparator 106 compares voltage 14 with the analog input voltage. Since the analog input voltage is lower in level than voltage 14, the 1-bit comparator 106 outputs xe2x80x9c0xe2x80x9d, as the conversion result. The control circuit 107 latches the conversion result in the bit 1 conversion cycle and outputs the control signal to set the comparison reference voltage to be used in the subsequent comparison, based on the conversion result. That is, the control circuit 107 outputs the control signal to the DAC 104 to set the comparison reference voltage to be used in bit 0 conversion cycle, based on the latched conversion result in the bit 3 conversion cycle, the latched conversion result in the bit 2 conversion cycle and the latched conversion result in the bit 1 conversion cycle. Assuming that the conversion result in the bit 3 conversion cycle is xe2x80x9c1xe2x80x9d and the conversion result in the bit 2 conversion cycle is xe2x80x9c1xe2x80x9d, if the conversion result in the bit 1 conversion cycle is xe2x80x9c1xe2x80x9d, voltage 15 is set by the control signal; if the conversion result in the bit 1 conversion cycle is xe2x80x9c0xe2x80x9d, voltage 13 is set by the control signal. Since, in this case, the conversion result in the bit 1 conversion cycle is xe2x80x9c0xe2x80x9d, voltage 13 is set as the comparison reference voltage to be used in the subsequent comparison.
Finally, in the bit 0 conversion cycle, the SAR 105 and the DAC 104 sets voltage 13 as the comparison reference voltage so that the 1-bit comparator 106 compares the comparison reference voltage with the analog input voltage. Since the analog input voltage is lower in level than voltage 13, the 1-bit comparator 106 outputs xe2x80x9c0xe2x80x9d as the conversion result. The control circuit 107 latches the conversion result in the bit 0 conversion cycle before completing the entire conversion process. An externally supplied control signal causes the final 4-bit conversion result to be output via the conversion result output terminal 12.
A disadvantage of the successive approximation A/D converter according to the related art is that the 1-bit conversion result yielded in each conversion cycle is output without being subjected to error detection. Since error correction adapted to incorrect conversion caused by cross talk, power source noise and the like is not provided, the converter according to the related art cannot adapt to high precision performance.
Accordingly, a general object of the present invention is to provide a successive approximation A/D converter in which the aforementioned disadvantage is eliminated.
Another and more specific object of the invention is to provide a successive approximation A/D converter capable of high precision performance in which an incorrect conversion is corrected.
The aforementioned objects can be achieved by a successive approximation A/D converter comprising an analog input terminal; a conversion result output terminal; voltage holding means connected to the analog input terminal and holding an analog input voltage input via the analog input terminal; voltage generating means for generating one or a plurality of voltages that serve as sources for producing comparison reference voltages subject to comparison with the analog input voltage; comparison reference voltage outputting means connected to the voltage generating means and outputting one or a plurality of comparison reference voltages in accordance with a control signal; comparing means comprising one or a plurality of comparators and comparing the analog input voltage with the one or the plurality of voltages output by the comparison reference voltage outputting means, so as to output a conversion result comprising at least 2 bits; and control means effecting error correction based on the conversion result output by the comparing means so as to output a final conversion result to the conversion result output terminal.
The comparing means may compare a first comparison reference voltage, a second comparison reference voltage lower than the first comparison reference voltage, a third comparison reference voltage with the analog input voltage, so as to output the conversion result xe2x80x9c11xe2x80x9d when the analog input voltage is higher than the first comparison reference voltage, output the conversion result xe2x80x9c10xe2x80x9d when the analog input voltage is lower than the first comparison reference voltage and higher than the second comparison reference voltage, output the conversion result xe2x80x9c01xe2x80x9d when the analog input voltage is lower than the second comparison voltage and higher than the third comparison reference voltage, output the conversion result xe2x80x9c00xe2x80x9d when the analog input voltage is lower than the third comparison reference voltage, output the conversion result xe2x80x9c1xe2x80x9d when the analog input voltage is higher than the first comparison reference voltage, where the first comparison reference voltage is the only voltage subject to comparison, and output the conversion result xe2x80x9c0xe2x80x9d when the analog input voltage is lower than the first comparison reference voltage, where the first comparison reference voltage is the only voltage subject to comparison, and the control means may process conversion of the analog input voltage into a n-bit digital value through cycles, where the comparison reference voltage is given in 2n steps, by outputting the control signal to the comparison reference voltage outputting means, thereby a) in a first conversion cycle, setting the first comparison reference voltage at a step 1*2nxe2x88x922, setting the second comparison reference voltage at a step 2*2nxe2x88x922, setting the third comparison reference voltage at a step 3*2nxe2x88x922, b) in an ith conversion cycle, where i=2xcx9cnxe2x88x921, setting the first comparison reference voltage in a previous conversion cycle as the second comparison reference voltage when the conversion result in the previous conversion cycle is one of xe2x80x9c11xe2x80x9d and xe2x80x9c10xe2x80x9d; setting the third comparison reference voltage in the previous conversion cycle as the second comparison reference voltage, setting a sum of the second comparison reference voltage in the previous conversion cycle and an increment of 2nxe2x88x92ixe2x88x921 in step as the first comparison reference voltage, and setting the second comparison reference voltage with a decrement of 2nxe2x88x92ixe2x88x921 in step subtracted therefrom as the third comparison reference voltage, when the conversion result in the previous conversion cycle is one of xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d, c) in a final nth conversion cycle, setting the first comparison reference voltage in the previous conversion cycle as the first comparison reference voltage, when the conversion result in the previous conversion cycle is one of xe2x80x9c11xe2x80x9d and xe2x80x9c10xe2x80x9d; setting the third comparison reference voltage in the previous conversion cycle as the first comparison conversion cycle, when the conversion result in the previous conversion cycle is one of xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d.
The comparing means may compare a first comparison reference voltage output from the comparison reference voltage outputting means and a second comparison reference voltage lower than the first comparison reference voltage also output from the comparison reference voltage outputting means with the analog input voltage, thereby outputting the conversion result xe2x80x9c10xe2x80x9d when the analog input voltage is higher than the first comparison reference voltage, outputting xe2x80x9c01xe2x80x9d when the analog input voltage is lower than the first comparison reference voltage and higher than the second comparison reference voltage, outputting xe2x80x9c00xe2x80x9d when the analog input voltage is lower than the second comparison reference voltage, outputting the conversion result xe2x80x9c1xe2x80x9d when the analog input voltage is higher than the first comparison reference voltage, where the first comparison reference voltage is the only voltage subject to comparison, and outputting xe2x80x9c0xe2x80x9d when the analog input voltage is lower than the first comparison reference voltage, where the first comparison reference voltage is the only voltage subject to comparison, and wherein the control means may process conversion of the analog input voltage into a n-bit digital value through cycles, where the comparison reference voltage is given in 2n steps, by outputting the control signal to the comparison reference voltage outputting means, thereby a) in a first conversion cycle, setting the first comparison reference voltage at a step 1*2nxe2x88x922 and setting the second comparison reference voltage at a step 3*2nxe2x88x922, b) in an ith conversion cycle, where i=2xcx9cnxe2x88x921, setting a sum of the first comparison reference voltage in a previous conversion cycle and an increment of 2nxe2x88x92ixe2x88x921 in step as the first comparison reference voltage, setting the first comparison reference voltage with a decrement of 2nxe2x88x92ixe2x88x921 in step subtracted therefrom as the second comparison reference voltage, when the conversion result in the previous conversion cycle is xe2x80x9c10xe2x80x9d; setting the first comparison reference voltage in the previous conversion cycle with a decrement of 2nxe2x88x92ixe2x88x921 in step subtracted therefrom as the first comparison reference voltage, setting a sum of the second comparison reference voltage in the previous conversion cycle and an increment of 2nxe2x88x92ixe2x88x921 in step as the second comparison reference voltage, when the conversion result in the previous conversion cycle is xe2x80x9c01xe2x80x9d; setting a sum of the second comparison reference voltage in the previous conversion cycle and an increment of 2nxe2x88x92ixe2x88x921 in step as the first comparison reference voltage, setting the second comparison reference voltage in the previous conversion cycle with a decrement of 2nxe2x88x92ixe2x88x921 in step subtracted therefrom as the second comparison reference voltage, when the conversion result in the previous conversion cycle is xe2x80x9c00xe2x80x9d, c) in a final nth conversion cycle, setting the first comparison reference voltage in the previous conversion cycle as the first comparison reference voltage, when the conversion result in the previous conversion cycle is xe2x80x9c10xe2x80x9d; setting the first comparison reference voltage in the previous conversion cycle with a decrement of 1 subtracted therefrom as the first comparison conversion cycle, when the conversion result in the previous conversion cycle is xe2x80x9c01xe2x80x9d; and setting the second comparison reference voltage in the previous conversion cycle as the first comparison reference voltage when the conversion result in the previous conversion cycle is xe2x80x9c00xe2x80x9d.
The comparing means may be comprised of one comparator.
The comparing means may be comprised of one comparator.
The successive approximation A/D converter may further comprise re-conversion means wherein, in the ith (i=1xcx9cnxe2x88x922) conversion cycle comprising the cycles for conversion of the analog input voltage into the n-bit digital value, a lower bit from the conversion result of the ith conversion cycle is compared with a higher bit from the conversion result in the conversion cycle subsequent to the ith conversion cycle so that, if the compared bits do not match, each of the ith conversion cycle and the subsequent conversion cycle is repeated at least once, a lower bit from the conversion result in the nxe2x88x921th conversion cycle is compared with a bit from the conversion result in the nth conversion cycle so that, if the compared bits do not mach, each of the nxe2x88x921th conversion cycle and the nth conversion cycle is repeated at least once.
The successive approximation A/D converter may further comprise conversion result validation means for determining a reference voltage corresponding to the digital value representing a final result of conversion, setting a predetermined range of voltages centered about the reference voltage, and determining whether the final result of conversion is valid based on comparison of voltages in the range with the analog input voltage.
The conversion result validating means may perform comparison in an increasing order of voltage levels for the voltages higher than the reference voltage and then performs comparison in a decreasing order for the voltages lower than the reference voltage.
The conversion result validating means may first perform comparison using the reference voltage and then alternately uses a higher voltage higher than the reference voltage and a lower voltage lower than the reference voltage in comparison in an increasing order of distance from the reference voltage.
The conversion result validating means may set an order of comparing voltages in the range with the analog input voltage, in accordance with a binary search scheme.